From cb0be9e2039569ee7d18657e8f675d1f8369b407 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Tue, 21 May 2024 13:50:28 +0200 Subject: restructured project --- rtl/src/alu.v | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 rtl/src/alu.v (limited to 'rtl/src/alu.v') diff --git a/rtl/src/alu.v b/rtl/src/alu.v new file mode 100644 index 0000000..8a265ee --- /dev/null +++ b/rtl/src/alu.v @@ -0,0 +1,47 @@ +module alu ( + input [31:0] a, + input [31:0] b, + + input [3:0] op, + + output reg [31:0] result, + output zero +); + +wire [31:0] arithmetic_result, logic_result, shift_result; + +arithmetic_unit au ( + .a(a), + .b(b), + .op(op[1:0]), + .result(arithmetic_result) +); + +logic_unit lu ( + .a(a), + .b(b), + .op(op[1:0]), + .result(logic_result) +); + +shift_unit su ( + .a(a), + .b(b[4:0]), + .op(op[1:0]), + .result(shift_result) +); + +`include "include/consts.vh" + +always @ (*) begin + case (op[3:2]) + ALU_OP_ARITHMETIC: result = arithmetic_result; // ARITHMETIC + ALU_OP_LOGIC: result = logic_result; // LOGIC + ALU_OP_SHIFT: result = shift_result; // SHIFT + default: result = 31'b0; + endcase +end + +assign zero = result == 32'b0; + +endmodule -- cgit v1.2.3