From 1ee5fc13995ee1383b0b75a19003b08fe33cfa54 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sat, 27 Apr 2024 14:59:48 +0200 Subject: added README --- README.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 README.md (limited to 'README.md') diff --git a/README.md b/README.md new file mode 100644 index 0000000..b56e854 --- /dev/null +++ b/README.md @@ -0,0 +1,12 @@ +# RISCV CPU + +An attempt at building a simple RISCV CPU in verilog. + +## Build + +* `make all` to synthesize, place and route the design and to generate the bitstream. +* `make program` to upload the bitstream to the FPGA. +* `make flash` to flash the bitsream to the FPGA. +* `make simulate` to run the testbench (sim/testbench.v). +* `make wave` to view the simulation in GTKWave. +* `make clean` to clean build files. -- cgit v1.2.3