From fefd558d0133b1c796de108d3be6cf579e262e7b Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Tue, 21 May 2024 07:57:08 +0200 Subject: updated README --- README.md | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index d98e570..9b2dabd 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,9 @@ # RISCV CPU -An attempt at building a simple RISCV CPU in verilog. +An attempt at building a simple RISCV CPU in verilog. Currently my CPU +implements the RV32I ISA without FENCE/ECALL/EBREAK instructions. The design +is very much based on David and Sarah Harris' book +"Digital Design and Computer Architecture (RISC-V Edition)". ## FPGA @@ -34,14 +37,14 @@ The board used in this project is a [Tang Nano 9K](https://wiki.sipeed.com/hardw ### Synthesis * [yosys](https://github.com/YosysHQ/oss-cad-suite-build) for synthesis -* [nextpnr-gowin](https://github.com/YosysHQ/apicula) for place and route +* [nextpnr-himbaechel](https://github.com/YosysHQ/apicula) for place and route * [gowin_pack](https://github.com/YosysHQ/apicula) for generating bitstream * [openFPGALoader](https://github.com/trabucayre/openFPGALoader) for uploading bitstream to FPGA ### Debugging * [gtkwave](https://github.com/gtkwave/gtkwave) for viewing waveforms -* [openocd](https://openocd.org) for debugging +* ([openocd](https://openocd.org) for debugging) ## Currently Supported Instructions -- cgit v1.2.3