From 08d6eea4fc23e7f569bbfd883f0dc049272a4b47 Mon Sep 17 00:00:00 2001
From: Flavian Kaufmann <flavian@flaviankaufmann.ch>
Date: Sat, 27 Apr 2024 14:52:08 +0200
Subject: added clock divider

---
 src/clock_divider.v | 27 +++++++++++++++++++++++++++
 src/top.v           | 12 ++++++++++--
 2 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 src/clock_divider.v

diff --git a/src/clock_divider.v b/src/clock_divider.v
new file mode 100644
index 0000000..499d8b2
--- /dev/null
+++ b/src/clock_divider.v
@@ -0,0 +1,27 @@
+module clock_divider #( 
+    parameter N = 2
+)(
+    input clk,
+    input reset,
+    output reg clk_out
+);
+
+    reg [31:0] counter = 0;
+
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            counter <= 0;
+            clk_out <= 0;
+        end else begin
+            if (counter == (N-1)/2) begin
+                clk_out <= ~clk_out;
+                counter <= counter + 1;
+            end else if (counter >= (N-1)) begin
+                clk_out <= ~clk_out;
+                counter <= 0;
+            end else begin
+                counter <= counter + 1;
+            end
+        end
+    end
+endmodule
diff --git a/src/top.v b/src/top.v
index 6fab4a6..845b17c 100644
--- a/src/top.v
+++ b/src/top.v
@@ -6,13 +6,21 @@ module top (
 
 reg [5:0] ctr_q;
 wire [5:0] ctr_d;
+wire clk_slow;
+assign reset = ~key;
 
-always @(posedge clk) begin
+clock_divider #(.N(10000000)) clk_div (
+  .clk(clk),
+  .clk_out(clk_slow),
+  .reset(reset)
+);
+
+always @(posedge clk_slow) begin
 	if (key) ctr_q <= ctr_d;
 	else ctr_q <= 6'b0;
 end
 
 assign ctr_d = ctr_q + 6'b1;
-assign led = ctr_q;
+assign led = ~ctr_q;
 
 endmodule
-- 
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