index
:
riscv_cpu.git
master
Simple RISC-V CPU written in Verilog
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
testvecs
/
testbench.vcd
Age
Commit message (
Collapse
)
Author
2024-05-01
read alu_testvec.txt from tests/
Flavian Kaufmann