| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-05-21 | restructured project | Flavian Kaufmann | |
| 2024-05-20 | reset synchronizer | Flavian Kaufmann | |
| 2024-05-20 | nextpnr himbaechel | Flavian Kaufmann | |
| 2024-05-15 | running c program | Flavian Kaufmann | |
| 2024-05-08 | view cpu waveform with make wave | Flavian Kaufmann | |
| 2024-05-08 | build assembly files | Flavian Kaufmann | |
| 2024-05-04 | added support for multiple testbenches | Flavian Kaufmann | |
| 2024-05-01 | added make target for testvec generation | Flavian Kaufmann | |
| 2024-04-27 | added README | Flavian Kaufmann | |
| 2024-04-27 | simulation | Flavian Kaufmann | |
| 2024-04-27 | initial commit | Flavian Kaufmann | |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
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