3 files changed, 36 insertions, 6 deletions

diff --git a/src/pc_reg.v b/src/pc_reg.v
index 2bdb540..11fe9ba 100644
--- a/src/pc_reg.v
+++ b/src/pc_reg.v
@@ -8,7 +8,7 @@ module pc_reg (
   output reg [31:0] pc
 );
 
-parameter PC_INITIAL = 32'h0001_0000;
+`include "include/consts.vh"
 
 always @ (posedge clk or negedge rstn) begin
   if (!rstn) pc <= PC_INITIAL;
diff --git a/src/reset_synchronizer.v b/src/reset_synchronizer.v
new file mode 100644
index 0000000..b957a4b
--- /dev/null
+++ b/src/reset_synchronizer.v
@@ -0,0 +1,22 @@
+module reset_synchronizer (
+    input clk,
+    input rstn_async,
+    output rstn
+);
+
+reg rstn_meta;
+reg rstn_sync_reg;
+
+always @(posedge clk or negedge rstn_async) begin
+  if (!rstn_async) begin
+    rstn_meta <= 1'b0;
+    rstn_sync_reg <= 1'b0;
+  end else begin
+    rstn_meta <= 1'b1;
+    rstn_sync_reg <= rstn_meta;
+  end
+end
+
+assign rstn = rstn_sync_reg;
+
+endmodule
\ No newline at end of file
diff --git a/src/top.v b/src/top.v
index fc1d9fe..b10fbca 100644
--- a/src/top.v
+++ b/src/top.v
@@ -1,23 +1,31 @@
 module top (
 	input clk,
 	input key,
+  input rst,
   output [5:0] led
 );
 
-wire rstn, clk_cpu;
-assign rstn = key;
+wire rstn, rstn_async, clk_cpu;
+assign rstn_async = rst;
 
 wire [31:0] io_in;
 wire [31:0] io_out;
 
+reset_synchronizer reset_synchronizer (
+  .clk(clk),
+  .rstn_async(rstn_async),
+  .rstn(rstn)
+);
+
 clock_divider #(.N(1)) clkdiv (
-    .clk(clk),
-    .rstn(rstn),
-    .clk_div(clk_cpu)
+  .clk(clk),
+  .rstn(rstn),
+  .clk_div(clk_cpu)
 );
 
 assign led[0] = ~clk_cpu;
 assign led[5:1] = ~io_out[4:0];
+assign io_in[0] = key;
 
 
 cpu cpu (