3 files changed, 9 insertions, 9 deletions
diff --git a/src/memory_unit.v b/src/memory_unit.v
index b2d7434..6e2b457 100644
--- a/src/memory_unit.v
+++ b/src/memory_unit.v
@@ -13,7 +13,7 @@ wire [31:0] ram_read_data, rom_read_data;
 ram #(.N(32), .SIZE(1024)) ram(
   .clk(clk),
   .rst(rst),
-  .we(we_ram),
+  .we(ram_we),
   .addr(addr),
   .data_read(ram_read_data),
   .data_write(write_data)
@@ -44,8 +44,8 @@ always @(*) begin
     read_data <= 0;
   end else if (addr[31:16] >= 16'h0001 && addr[31:16] <= 16'h000F) begin
     read_data <= rom_read_data;
-    ram_we = we;
   end else if (addr[31:16] >= 16'h0010 && addr[31:16] <= 16'hFF0F) begin
+    ram_we = we;
     read_data <= ram_read_data;
   end else if (addr[31:16] >= 16'hFF10 && addr[31:16] <= 16'hFFFF) begin
     read_data <= 0;
diff --git a/src/ram.v b/src/ram.v
index 92b14a2..9b62c77 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -7,23 +7,25 @@ module ram #(
     input we,
     input [log2(SIZE)-1:0] addr,
     input [N-1:0] data_write,
-    output reg [N-1:0] data_read
+    output [N-1:0] data_read
 );
 
 `include "include/log2.vh"
 
 reg [8:0] memory [SIZE-1:0];
 
+assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
+
+
 integer i;
 always @(posedge clk or posedge rst) begin
   if (rst) begin
     for (i = 0; i < SIZE; i = i + 1)
       memory[i] <= 0;
-  end else begin
+  end else begin 
     if (we) begin
       { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
     end
-    data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
   end
 
 end
diff --git a/src/rom.v b/src/rom.v
index a2e12cd..8a25f46 100644
--- a/src/rom.v
+++ b/src/rom.v
@@ -4,7 +4,7 @@ module rom #(
 )(
     input clk,
     input [log2(SIZE)-1:0] addr,
-    output reg [N-1:0] data_read
+    output [N-1:0] data_read
 );
 
 `include "include/log2.vh"
@@ -15,9 +15,7 @@ initial begin
   $readmemh("build/rom.hex", memory, 0, SIZE-1);
 end
 
-always @(posedge clk) begin
-  data_read <= {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
-end
+assign data_read = {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };