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-rw-r--r--src/register_file.v26
1 files changed, 11 insertions, 15 deletions
diff --git a/src/register_file.v b/src/register_file.v
index de697ab..5142a69 100644
--- a/src/register_file.v
+++ b/src/register_file.v
@@ -1,27 +1,23 @@
-module register_file #(
- parameter N = 32,
- parameter XLEN = 32
-)(
+module register_file (
input clk, rst, we,
- input [log2(XLEN)-1:0] addr_read0, addr_read1, addr_write2,
- input [N-1:0] data_write2,
- output reg [N-1:0] data_read0, data_read1
+ input [4:0] rs1, rs2, rd,
+ input [31:0] rd_data,
+ output reg [31:0] rs1_data, rs2_data
);
-`include "include/log2.vh"
-reg [N-1:0] registers[XLEN-1:1];
+reg [31:0] registers[31:1];
integer i;
always @(posedge clk or rst) begin
if (rst) begin
- for (i = 1; i < XLEN; i = i + 1)
- registers[i] <= 0;
+ for (i = 1; i < 32; i = i + 1)
+ registers[i] <= 32'b0;
end else begin
- data_read0 = (addr_read0 == 0) ? 0 : registers[addr_read0];
- data_read1 = (addr_read1 == 0) ? 0 : registers[addr_read1];
- if (we && (addr_write2 != 0)) begin
- registers[addr_write2] <= data_write2;
+ rs1_data = (rs1 == 0) ? 32'b0 : registers[rs1];
+ rs2_data = (rs2 == 0) ? 32'b0 : registers[rs2];
+ if (we && (rd != 0)) begin
+ registers[rd] <= rd_data;
end
end
end