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-rw-r--r--src/arithmetic_unit.v9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/arithmetic_unit.v b/src/arithmetic_unit.v
index be087a7..64ec0f9 100644
--- a/src/arithmetic_unit.v
+++ b/src/arithmetic_unit.v
@@ -3,21 +3,20 @@ module arithmetic_unit #(
)(
input [N-1:0] A, B,
input [1:0] OP, // 00: ADD, 01: SUB, 11: SLT
- output [N-1:0] RESULT,
- output OVERFLOW
+ output [N-1:0] RESULT
);
wire [N-1:0] b, sum;
-wire cin, altb;
+wire cin, altb, overflow;
assign b = OP[0] ? ~B : B;
assign cin = OP[0];
assign sum = A + b + cin;
-assign OVERFLOW = ~(A[N-1] ^ B[N-1] ^ OP[0]) & (A[N-1] ^ sum[N-1]);
+assign overflow = ~(A[N-1] ^ B[N-1] ^ OP[0]) & (A[N-1] ^ sum[N-1]);
-assign altb = OVERFLOW ^ sum[N-1];
+assign altb = overflow ^ sum[N-1];
assign RESULT = OP[1] ? {{(N-1){1'b0}}, altb} : sum;